The present invention relates to a monolithic semiconductor integrated circuit having a transistor circuit block constituted by a driving MISFET and a load MISFET.
A MISFET circuit which can be operated by a power source voltage higher than the breakdown voltage between the drain and the source of the MISFET has been publicly known as shown in Japanese Patent Publication No. 32450/1974. This MISFET circuit includes two MISFETs. The source of one FET is connected in series to the drain of the other FET, while a reference voltage and an input signal are applied to the source and the gate of the other FET. The drain of the one FET is connected through a load resistance to a power voltage supply terminal, while the gate of the same receives a voltage higher than the threshold voltage.
Another type of MISFET circuit is disclosed in the specification of U.S. Pat. No. 4,016,430, in which the source of a depletion type MISFET is connected in series to the drain of the other MISFET, while the source and gate of the other MISFET receive a reference voltage and an input signal, respectively. The drain of the depletion type FET is connected through the load MISFET to the power source voltage terminal, while the gate of the same receives the reference voltage.
According to the study by the inventors of the present invention, it becomes clear that the prior arts explained herein before have the following disadvantages.
(1) Supposing that the load resistance in the MISFET circuit disclosed in Japanese Patent Publication No. 32450/1974 is substituted by a load MISFET and that the two FETs are formed in a monolithic semiconductor integrated circuit together with this load FET, the PN junction between the drain and the semiconductor substrate just beneath the gate insulation film of the load FET breaks down by a high voltage applied to the power source voltage terminal, depending on the condition of the voltage applied to the gate of the load FET.
(2) Turning now to the technique as shown in the specification of U.S. Pat. No. 4,016,430, the PN junction between the drain and the substrate breaks down at the semiconductor surface just below the gate insulating film of the load FET, as is the case of the above mentioned known technique, depending on the condition of the voltage applied to the gate of the load FET, when a high voltage is applied to the power voltage supply terminal of the MISFET circuit.
(3) There have been proposed some methods of improving the breakdown voltage of the PN junction between the drain and the substrate on the semiconductor surface just below the gate insulation film of the MISFET.
One of these methods is shown at pages 50 to 61 of "Electronics" published on Nov. 30, 1964, in which a MISFET of a high breakdown voltage having an offset gate construction is used. The IBM Technical Disclosure Bulletin Vol. 16, No. 5 (pp 1635-1636) published in October 1973 teaches the use of a MISFET of high breakdown voltage, in which an auxiliary semiconductor region having a impurity concentration lower than that of the source and drain regions is formed just beneath the gate electrode.
These MISFETs having improved breakdown voltage characteristics are however large in size, so that, when each of a large number of load MISFETs of a transistor logic circuit block of a monolithic semiconductor circuit is constituted by this large-sized MISFET, the density of integration of the monolithic semiconductor circuit is inconveniently lowered.